核心代码片段（Verilog状态机）：

// I2C主控状态机 - 读取SFP EEPROM
localparam IDLE      = 4'd0;
localparam START     = 4'd1;
localparam SEND_ADDR = 4'd2;
localparam SEND_REG  = 4'd3;
localparam RESTART   = 4'd4;
localparam READ_DATA = 4'd5;
localparam STOP      = 4'd6;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        state <= IDLE;
        // ... 其他寄存器清零
    end else begin
        case (state)
            IDLE: begin
                if (start_read) begin
                    state <= START;
                    scl_out <= 1'b1;
                    sda_out <= 1'b1;
                end
            end
            START: begin
                // 拉低SDA，产生起始条件
                sda_out <= 1'b0;
                state <= SEND_ADDR;
            end
            SEND_ADDR: begin
                // 发送0xA0，等待ACK
                // ... 移位发送逻辑
                if (ack_received) state <= SEND_REG;
            end
            SEND_REG: begin
                // 发送寄存器地址，比如0x00
                // ... 移位发送逻辑
                if (ack_received) state <= RESTART;
            end
            RESTART: begin
                // 产生重启条件
                sda_out <= 1'b1;
                scl_out <= 1'b1;
                state <= READ_DATA;
            end
            READ_DATA: begin
                // 读取8位数据，每读一位拉低SCL
                // ... 移位接收逻辑
                if (byte_done) begin
                    data_reg <= {data_reg[6:0], sda_in};
                    if (last_byte) begin
                        sda_out <= 1'b1; // NACK
                        state <= STOP;
                    end else begin
                        sda_out <= 1'b0; // ACK
                    end
                end
            end
            STOP: begin
                sda_out <= 1'b0;
                scl_out <= 1'b1;
                sda_out <= 1'b1; // 停止条件
                state <= IDLE;
                read_done <= 1'b1;
            end
        endcase
    end
end

实际项目经验：我遇到过一种情况，读回来的DDM数据全是0xFF。一开始以为是I2C时序问题，折腾了半天。后来发现是模块的电源没供上。所以，读DDM之前，先确认模块的电源和使能信号都正常。